Evolutionary Mapping of Neural Networks to Spatial Accelerators
Abstract
Spatial accelerators, composed of arrays of compute-memory integrated units, offer an attractive platform for deploying inference workloads with low latency and low energy consumption. However, fully exploiting their architectural advantages typically requires careful, expert-driven mapping of computational graphs to distributed processing elements. In this work, we automate this process by framing the mapping challenge as a black-box optimization problem. We introduce the first evolutionary, hardware-in-the-loop mapping framework for neuromorphic accelerators, enabling users without deep hardware knowledge to deploy workloads more efficiently. On Intel's Loihi 2, our method achieves up to 35% reduction in total latency compared to default heuristics on two sparse multilayer perceptron networks. We further demonstrate the scalability of our approach to multi-chip systems and observe an up to 40% gain in energy efficiency, without explicitly optimizing for it.
Details
- Organisationseinheit(en)
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Fachgebiet Maschinelles Lernen
- Externe Organisation(en)
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Ludwig-Maximilians-Universität München (LMU)
Intel Deutschland GmbH
Harvard University
Intel Corporation
Munich Center for Machine Learning (MCML)
Deutsches Forschungszentrum für Künstliche Intelligenz GmbH (DFKI)
- Typ
- Aufsatz in Konferenzband
- Seiten
- 329-337
- Anzahl der Seiten
- 9
- Publikationsdatum
- 10.07.2026
- Publikationsstatus
- Veröffentlicht
- Peer-reviewed
- Ja
- ASJC Scopus Sachgebiete
- Artificial intelligence, Theoretische Informatik und Mathematik, Angewandte Informatik, Steuerung und Optimierung, Logik
- Elektronische Version(en)
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https://doi.org/10.1145/3795095.3805135 (Zugang:
Offen
)
